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_______________________________ | | | DESIGN CENTER - SYSTEM 3 | EVALUATION VERSION | 5.3 RELEASE | |_______________________________| This file describes any enhancements or modifications made to the Evaluation version of the 5.3 release of the Design Center - System 3 and covers new information for the IBM-PC Microsoft Windows, and Sun OpenWindows platforms. The Design Center - System 3 Evaluation version includes Schematics, PSpice, Probe, the Stimulus Editor, and Parts programs. Information regarding new material for these programs and any material which did not make it into the manuals is provided in this file. With the Design Center - System 3 Evaluation version, the Schematic Editor is limited to one page schematics, A-size pages only, and a maximum placement of 20 parts on the page. The maximum circuit size is 64 nodes and 10 active components (or approximately 2 opamps). Only a subset of our Model and Symbol Library is included, and the device characterization utility is limited to modeling diodes. The Design Center - System 3 manual set includes the following: Schematic Capture User's Guide Circuit Analysis User's Guide Circuit Analysis Reference Manual Circuit Analysis System Setup Manual Design Center Application Notes Manual These Manuals will be referenced throughout this file. If you would like to purchase the manuals or the complete production version of the Design Center, please call MicroSim at (800) 245-3022. **************************************************************************** MicroSim Corporation now offers the Technical Support Bulletin Board System (BBS). On the BBS you will find information regarding the operation of our Design Center systems. You can request new literature packages, and use the Message utility to let us know your comments and suggestions. The BBS supports several different terminal types, but is basically set up for the 80 character wide, 24 line, ANSI and VT100/VT102 terminal emulation. You may log on to the system as often as you like, but logon time is limited to 60 minutes per day. The system will automatically log you off when left idle for 5 minutes. We encourage you to log on and have a look around! To access our BBS, dial: 714-454-7611 { 9600-1200, N-8-1 } ********************************************************************* Table of Contents ********************************************************************* ** SCHEMATICS ** 1.0 Editing Model Definitions in Schematics 2.0 Specifying Digital Power Supplies 2.1 Using the Stimulus Generator and File Stimulus Device in Schematics 2.2 HI and LO digital nets 3.0 Interfacing to External Layout Packages 3.1 Protel for Windows 4.0 Schematic Editor New Menus and Menu Items 4.1 Edit Menu 4.2 Navigate Menu 4.3 Configure Menu 4.4 Analysis Menu 4.5 Tools Menu (New Menu) 5.0 Symbol Editor New Menus and Menu Items 5.1 Edit Menu 5.1.1 Changes to the "Pinlist" and "Change Pin" dialogs 5.2 Packaging Menu (New Menu) 6.0 Layout Mapping Files 7.0 Library Expansion and Compression Utilities 8.0 Parts With Unmodeled Pins 8.1 How the PSpice Netlister Handles Unmodeled Pins 8.2 Floatable Pins 8.3 Implementation of Unmodeled and Floatable Pins 9.0 Attribute Values and Hierarchy in Schematics 10.0 Known Problems and Workarounds 10.1 Hidden Pin Display 11.0 Example Schematics 11.1 example.sch 11.2 osc.sch ** PSPICE ** 1.0 PSpice Commands 1.1 .MODEL 1.2 GaAsFET, Capacitor, Diode, JFET, Inductor, MOSFET, Bipolar Transistor, and Resistor (new parameters) 1.3 Voltage-Controlled Voltage Source (additional general form) 1.4 .OPTIONS 1.5 .FUNC 2.0 PSpice Model Library Changes 3.0 Miscellaneous Changes to PSpice Simulation 3.1 Flip-Flops and Latches 3.2 Timing Violations 3.3 Pin-to-Pin Delay 3.4 Constraint Check 3.5 Limits on Mutual Inductance 3.6 Using the Charge Storage Feature of PSpice Digital Simulation 4.0 CMOS Power Supplies 4.1 Specifying Your Own Power Supply 5.0 Digital Device I/O Model Parameter Updates 6.0 Remodeled Digital Devices and Timing Capabilities 7.0 Simulation Condition Messages 8.0 Charge Conservation ** PROBE ** 1.0 Probe New Menu Structure ********************************************************************* SCHEMATICS ********************************************************************* Note on transferring files between PC and Sun computers Both symbol library files (.slb) and schematic files (.sch) include a byte count and should therefore NOT be modified using a text editor. When transferring files from one system to the other, you must transfer the file in binary mode (not ASCII). 1.0 Editing Model Definitions in Schematics Schematics now supports Monte Carlo, Worst-Case, and model editing by providing a mechanism for manipulation of .MODEL and .SUBCKT definitions of parts. Schematics allows you to edit model definitions, create new models, associate model definitions with symbols, or derive new model definitions from existing ones. For information on the implementation of model editing in the Schematic Editor and Symbol Editor, refer to Chapter 5, Section 5.4 of the Schematic Capture User's Guide. Section 5.4.7 includes an example of model editing using Monte Carlo analysis. 2.0 Specifying Digital Power Supplies Section 5.9 (starting on page 108) in the Schematic Capture User's Guide describes how to change the power supply on devices from the digital symbol libraries. 2.1 Using the Stimulus Generator and File Stimulus Device in Schematics There are two ways to specify a digital input signal in Schematics. One is to use the file stimulus device, FSTIM. The other is to use a digital stimulus generator. The file stimulus device is used to access one or more signals inside a stimulus file. The Schematics symbol for the file stimulus is called FileStim and is in the SOURCE.SLB symbol library. Double-click on the symbol to enter values for the FileName and SigName attributes. FileName is the name of your stimulus file, and SigName is the name of the signal. After connecting the FileStim device to the input node of the circuit, you can use the Notepad text editor in Windows to create the stimulus file. The following is an example of a stimulus file and shows the proper format: CLOCK 0 0 20ns 1 40ns 0 60ns 1 80ns 0 Another way to specify a digital input is to use a digital stimulus. The digital stimulus generator allows you to create a variety of digital signals using simple commands. To use the digital stimulus requires a few more steps than to use the FSTIM method. Place a GLOBAL symbol from the PORT.SLB symbol library at the digital input node of the circuit. Label the node by double-clicking on the GLOBAL symbol. The label should be the same name as the node name in the digital stimulus file. You can use the Notepad text editor in Windows to create the digital stimulus file. The digital stimulus file has the following format: U<name> STIM(<width>,<format array>) + <digital power node> <digital ground node> + <node>* + <I/O Model name> + [IO_LEVEL= <interface subckt select value>] + [TIMESTEP=<stepsize>] + <command> Here is an example of a digital stimulus: UCLK STIM(1,1) $G_DPWR $G_DGND + CLOCK + IO_STM + 0S 0 + LABEL=CYCLE + +20NS 1 + +20NS 0 + +20NS GOTO CYCLE -1 TIMES After saving the digital stimulus file, use the INCLUDE symbol from SPECIAL.SLB to include the filename of the digital stimulus. Both the digital stimulus generator and the file stimulus device are discussed in more detail in chapter 7.4 of the Circuit Analysis User's Guide. 2.2 HI and LO digital nets The HI and LO port symbols enable you to speed up digital simulation when you want a digital pin tied high or low. These symbols may be used across all digital families and will provide a logic 1 or 0. These symbols are not useable for PCB design, however. You will need to replace them with a resistor, if appropriate, and a connection to power or ground. 3.0 Interfacing to External Layout Packages Schematics currently supports netlisting for the PADS and Protel PCB layout editor formats. The layout netlists produced by Schematics can be used as input to any external PCB layout package that accepts these formats. Schematics also supports file-based backward Engineering Change Orders (ECOs) in the PADS layout editor format. That is, ECO files produced by the layout packages can be read by Schematics to back annotate the schematic. Schematics can also be configured to directly invoke an external layout editor from within the schematic environment. See Chapter 8 of the Schematic Capture User's Guide for more information on Schematics' interface to external layout editors and how to package schematics. 3.1 Protel for Windows In addition to supporting the PADS board layout system, Schematics also supports Protel for Windows. To select Protel as the layout editor, invoke Tools/Configure Layout Editor, click in the 'Layout Netlist' combo box, and select PROTEL. You may also configure the command line used to invoke the editor in the same dialog. Schematics will produce a netlist in native Protel format. Three mapping files ("protel.xmp," "protel.xpk," and "protel.xnt") translate Schematics output to Protel-specific names (for example, Protel has a package type 'TO-3' which is 'TO3' to Schematics). Protel does not have an ECO mechanism, so Schematics does not provide an ECO function when used with Protel. Many of the package types used by analog parts in the PSpice libraries are not present in the Protel pattern library (for example, there is no 'TO-61' pattern). 4.0 Schematic Editor New Menus and Menu Items 4.1 Edit Menu (new commands) Model allows you to edit the PSpice .MODEL or .SUBCKT definition for a part. For complete instruction on using the Edit/Model command, see page 166 of the Schematic Capture User's Guide. Change Model Reference brings up a dialog that allows you to enter the name of another model for this part instance. See page 167 of the Schematic Capture User's Guide for more information on this command. Edit Instance Model allows you to edit a copy of the model or subcircuit definition. See page 167 of the Schematic Capture User's Guide for more information on this command. 4.2 Navigate Menu (new commands) Edit Schematic Instance allows you to view the instance-specific attributes associated with the instance of the block or hierarchical symbol into which you are pushed. See page 172 of the Schematic Capture User's Guide for more information on this command. Edit Schematic Definition allows you to edit the underlying schematic into which you are pushed. Changes made will affect all instances of hierarchical blocks and symbols that reference this schematic. This command is available only if you have pushed into a subschematic. 4.3 Configure Menu The Library Settings dialog box has been changed. If the library you are adding is a symbol or package library, click in the box respective to the file type, and the default extension will appear. See page 176 of the Schematic Capture User's Guide for an illustration of the new dialog. 4.4 Analysis Menu (new commands and changes) Annotate assigns reference designators to parts, or deletes previous annotations. See pages 177-179 of the Schematic Capture User's Guide for information on using the commands in this dialog. Setup brings up a dialog which allows you to enable, disable, and select PSpice analyses. To enable an analysis type, click in the Enabled box to the left of the button of the desired analysis. This will put a small "x" in the box indicating that the analysis is turned on. When the box is empty, the analysis is disabled. Pressing OK will exit this dialog. Library and Include Files allows you to specify files to be included or referenced in the PSpice netlist. See page 193 of the Schematic Capture User's Guide for information on using this command. 4.5 Tools Menu (new menu) The Tools Menu allows you to interface to external layout editors. You can create netlists that can be used as input to your layout editor, and apply backward ECO's generated by the layout editor to the schematic. For details on the new Tools Menu and the commands, see pages 194-195 of the Schematic Capture User's Guide. Tools/Configure Layout Editor Command Line Command Line specifies the command to be invoked when the Tools/Layout Editor menu item is chosen. This command may contain the following special sequences on the command line: Code Description %c current working directory %e schematic name without extension %f entire name %n schematic name without extension or path For example, if the schematic c:\msim53\example.sch is the currently loaded schematic, then the following text is substituted in the command line in place of the special codes: %c c:\msim53 %e c:\msim53\example %f c:\msim53\example.sch %n example 5.0 Symbol Editor New Menus and Menu Items 5.1 Edit Menu (new command) Model allows you to edit the PSpice .MODEL or .SUBCKT definition for a part. From within the Symbol Editor, the "global" model or subcircuit representation is edited. By default theses changes are saved in a file called "user.lib." Changes made to the model or subcircuit in the Symbol Editor will affect all the parts that use this model or subcircuit. See pages 211-213 in the Schematic Capture User's Guide for information on using the Edit/Model command in the Symbol Editor. 5.1.1 Changes to the "Pin List" and "Change Pin" Dialogs The Pin List and Change Pin dialogs (Part/Pinlist and Edit/Change) have a new checkbox and a new list box in the Pin Attributes section. The checkbox is labeled "Modeled Pin" and is checked by default. If the pin is modeled, this box should be checked. If the pin is NOT part of the simulation model (such as balance and offset pins on some opamps), then the box should be unchecked. When the box is unchecked, the pin is marked as not simulated and a "FLOAT=u" attribute is applied to the pin. This allows the PSpice netlister to pay special attention to the pin in case there are fewer than two connections at its node. In that case, a large resistor to ground is added for simulation purposes. If the checkbox is unmarked, the "FLOAT=" list box is not enabled, as noted by the "If Unconnected:" label. However, if it is marked, the list box is enabled. This allows you to pick a default action that the PSpice netlister will take in the event that you have not connected this pin to any others. The choices are "RtoGND", "UniqueNet" and "Error". Selecting "RtoGND" will tell the netlister to add a large resistor to ground for the pin. Selecting "UniqueNet" will cause a unique node to be generated for the pin which can be used for seeing its trace in Probe by adding a marker. Selecting "Error" will cause the netlister to fail with an "Unconnected Pin" error message if the pin is not connected to any others. (See also Section 9.0 "Parts With Unmodeled Pins" in the SCHEMATICS section of this file.) 5.2 Packaging Menu (new menu) The Packaging Menu allows you to edit package definitions in the package library corresponding to the current symbol library. Within this menu you can edit package types, gate types, pin assignments, shared pins, and attributes associated with the package definitions. For information on the new commands in the Packaging Menu, see pages 220-223 in the Schematic Capture User's Guide. 6.0 Layout Mapping Files Mapping files contain rules for translating from Schematics to layout system identifiers. Map files exist for each of the layout formats supported. See Appendix B in the Schematic Capture User's Guide for information on mapping files. The operation of the ` (backquote) character in layout netlist mapping entries has been changed from what is currently written in the Schematic Capture User's Guide. It now operates as a modifier on 'special characters' such as '@'. It still means "the value of the attribute when translated by a rule in the .xmp file". The table below shows the special character-attribute syntax with and without the backquote modifer: @<id> replaced by value of <id>. Error if no such attribute or no value. @`<id> replaced by mapped value of <id>. Same error conditions. &<id> replaced by value of <id> if <id> defined. &`<id> replaced by mapped value of <id> if <id> defined. 7.0 Library Expansion and Compression Utilities The library expansion utility lx (lx.exe on the PC, lx on the Sun) and the library compression utility lc (lc.exe on the PC, lc on the Sun) are provided with the Design Center - System 3 package. These utilities work with both symbol and package libraries. They can be used for: - salvaging a corrupted library - maintaining library files - reorganizing a library - creating a batch library For information on how to use the library expansion and compression utilities, refer to Appendix C of the Schematic Capture User's Guide. 8.0 Parts with Unmodeled Pins The Schematics symbol libraries have been updated to include pins that are not modeled by the parts in the corresponding PSpice model libraries. These include pins for offset nulling, etc. Such pins are termed "unmodeled" pins. Schematics will display an unmodeled pin with a break in the graphics for the pin. That is, a regular pin is displayed as '---' (a solid pin), whereas an unmodeled pin is displayed as '- -' (a broken pin). This distinction applies only to the display of these pins in Schematics; i.e., these pins will appear as [regular] solid pins when you print/plot to your hardcopy device. Parts which have been changed for the 5.3 release include operational amplifiers in the analog libraries, and one-shots in the digital libraries. Where possible, the location of existing pins has not been changed such that an existing schematic can be read in without changes. Please see Section 8.0 "Library Changes" of this readme for a list of affected parts. 8.1 How the PSpice Netlister Handles Unmodeled Pins If an unmodeled pin is left floating (i.e., no connections are made to it), no PSpice netlist entries will be generated referring to that pin. If connections are made to an unmodeled pin, Schematics will issue an ERC warning but will proceed to generate a netlist. A large value resistor will be added to the netlist between the net connecting to the pin and analog ground. The netlist line for this resistor is of the form R__UC<number> <node> 0 <value> The <value> field defaults to {1/GMIN}. This can be modified by setting LARGERESISTOR in the [SCHEMATICS] section of msim.ini to the desired value. Note that GMIN is one of PSpice's built-in global parameters. Its value can be modified by using the Analysis/Setup/Options dialog in Schematics. The default value will result in a resistor of value 1E12 ohms. 8.2 Floatable Pins The Schematics Symbol library has been modified to allow pins on digital symbols to float. This is considerably more convenient than having to connect unused pins to the "NC" pseudocomponent. It also allows digital levels at these pins to be viewed by placing a Probe marker on the pin. When a "floatable" digital pin is left unconnected, the netlister will connect that pin to a unique net. No other pins will be connected to this net. It is also possible to specify that a pin is floatable and analog. For floatable analog pins, a large value resistor will be added to the netlist between the pin and analog ground, when the pin is left floating. [See above section for details]. 8.3 Implementation Of Unmodeled and Floatable Pins Please see the Section 5.1.1 of this readme file for details. Note that if a pin is defined to be unmodeled, there should be no reference to the pin in the PSpice netlist TEMPLATE. 9.0 Attribute Values and Hierarchy in Schematics A number of changes have been made to the way that attributes are evaluated in Schematics. First, if an attribute is not found at the current level of hierarchy, then the parent level is searched for a definition, continuing up the hierarchy until either a definition is found or the top of the hierarchy is reached. (Previous versions of Schematics searched only the immediate parent's environment.) Secondly, when an attribute is found, it is evaluated at the level where it was found. If the attribute value contains further attributes, these must exist at the current level or higher in the hierarchy. For example, suppose that we have an instance of a hierarchical symbol 'A' which has defines two attributes: X=@Y and Y=10. Suppose also that A contains an instance of a symbol 'B': B contains an expression referring to the attribute X and defines the value of attribute Y to be 20. ----------------------- | A | X=@Y | | Y=10 | --------- | | | B | | | | {@X} | | | | Y=20 | | | --------- | ----------------------- Evaluation of the expression {@X} takes place as follows. The current level is searched for X. There is no X attribute at this level, so the parent environment (part A) is searched. An attribute named X is found at this level. This attribute is evaluated IN THE ENVIRONMENT SUPPLIED BY A. The first stage of this evaluation delivers the result "@Y". This is then processed to yield the result "10". The final result is to make the result of the expression be "{10}". Note that the definition for Y in the environment supplied by part B must not be used when evaluating X in A's environment. (Previous versions of Schematics did this.) In practice this means that the limitation where attributes were looked for in only one level of hierarchy above the current level has been removed. This makes it possible to parameterize hierarchical blocks and symbols without concern for how deeply their contents are nested. 10.0 Known Problems and Workarounds 10.1 Hidden Pin Display The display of hidden pins will incorrectly be turned on when you use the Edit/Push command from within the Symbol Editor, Navigate/Pop when finished, and then return from the Symbol Editor to the Schematic Editor and exit. The workaround is to use Configure/Set Display Level to reset the display of hidden pins to OFF before you exit. 11.0 Example Schematics 11.1 example.sch example.sch is a differential pair, and shows many of the capabilities of PSpice. Select Analysis/Setup to examine some of the different ways PSpice can analyse this circuit. The AC Sweep button will show you the AC and NOISE analysis setup. The real and imaginary response of the circuit is calculated as the inputs are swept from 100 kilohertz to 10 gigahertz by decades with 10 points per decade. The only AC input this circuit has is V1. This is a linear analysis. Enabling NOISE analysis (with AC analysis enabled) will cause PSpice to do noise calculations during the AC analysis. Each device's noise contribution is calculated and propogated to node OUT2. All the contributions are rms-summed at node OUT2. Besides the total output noise printout done for every frequency, a detailed table of each device's contribution is done every 30'th frequency. The DC Sweep button shows you the setup for DC analysis. The voltage source V1 is swept from -0.125 volts to 0.125 volts in steps of 0.005 volts. The non-linear device equations are used. Pushing the Temperature button (with enabled checked) tells you that PSpice is being told to simulate the circuit at 35 degrees Celcius. Push the Transfer Function button to see the setup for doing a small-signal transfer function calculation assuming V1 is the input and V(OUT2), the voltage at node OUT2, is the output. The Transient button (enabled) causes PSpice to do a transient analysis. PSpice first re-calculates the circuit's bias point, then calculates the circuit's time response from 0 nanoseconds to 5 microseconds using the full, non-linear device equations, including non-linear capacitances. PSpice uses a variable time step for the calculations, but this command causes the results to be interpolated onto a 20 nanosecond print interval. Transient analysis is the most frequently used analysis in PSpice. The Fourier Analysis (enabled within the Transient dialog) tells PSpice to do a harmonic decomposition on the waveform V(OUT2) calculated during transient analysis. It calculates the magnitude and phase of the fundamental (1 megahertz) and the first eight harmonics. The graphics post-processor, Probe, goes further and contains a full FFT, allowing complete spectra to be displayed. 11.2 osc.sch osc.sch is a mixed-mode ring-oscillator circuit. It consists of a pair of schmitt-trigger inverters, a 2K resistor, a 400pF capacitor. A digital stimulus is used to start the oscillation and clear the toggle flip-flop at the output. The 74LS05 open-collector inverter floats after the initial 0 pulse occurs. ********************************************************************* PSPICE ********************************************************************* 1.0 PSpice Commands 1.1 .MODEL PSpice now allows for the customization of model temperature for passive and semiconductor devices. There are two levels of temperature attributes which can be customized on a model by model basis; the temperature at which the model parameters are assumed to be measured and current device temperatures. See page 60, and pages 62-64 of the Circuit Analysis Reference Manual for information on temperature customization. 1.2 GaAsFET, Capacitor, Diode, JFET, Inductor, MOSFET, Bipolar Transistor, and Resistor (new parameters) Model Param. Description Units Default ------------ ----------------------------------- -------- ------- T_MEASURED Measured temperature degrees C T_ABS Absolute temperature degrees C T_REL_GLOBAL Relative to current temperature degrees C T_REL_LOCAL Relative to AKO model temperature degrees C For information on these parameters, see the discussion above about the .MODEL statement. 1.3 Voltage-Controlled Voltage Source (additional general form) E<name> <(+) node> <(-) node> CHEBYSHEV { <expression> } = + <[LP] [HP] [BP] [BR]>,<cutoff frequencies>*,<attenuation>* Chebyshev filters have two attenuation values, given in dB, which specify the pass band ripple and the stop band attenuation. They may be given in either order, but must appear after all of the cutoff frequencies have been given. Low pass (LP) and high pass (HP) have two cutoff frequencies, specifying the pass band and stop band edges, while band pass (BP) and band reject (BR) filters have four. Again, these may be given in any order. 1.4 .OPTIONS Command .OPTIONS (new options) Option Meaning Units Default ------ ----------------------------------- ----- ------- NOOUTMSG Suppress simulation error messages in output file. NOPRBMSG Suppress simulation error messages in Probe data file DIGERRDEFAULT Default error limit for digital constraint devices DIGERRLIMIT Maximum digital error message limit infinite 1.5 .FUNC Please note that the .FUNC statement expects its arguments to be of numerical values (such as V(a) or V(5)) instead of numerical forms of the names (such as node names). The example on page 43 of the Design Center Application Notes Manual does not work. The following information should be changed: Change .FUNC vsq(node) v(node)*v(node) to .FUNC vsq(nodev) nodev*nodev Change g1 vd 0 value {k*((-v(vo)*v(vf))+(ve(vo,vd,va)*v(vd)))} to g1 vd 0 value {k*((-v(vo)*v(vf))+(ve(v(vo),v(vd),v(va))*v(vd)))} 2.0 PSpice Model Library Changes See Section 8.1 of the SCHEMATICS Section of this file. 3.0 Miscellaneous Changes to PSpice Simulation 3.1 Flip-Flops and Latches X-Level Handling The truth-table for each type of flip-flop and latch is given on page 206 of the Circuit Analysis Reference Manual. 3.2 Timing Violations The Circuit Analysis Reference Manual now describes the conditions such as timing violations, which cause the flip-flop and latch primitives to change their outputs to X. In addition, the truth tables for each type have been added. Refer to page 206 for more information. 3.3 Pin-to-Pin Delay The PINDLY primitive has been enhanced to model tri-state output behavior. Refer to pages 236-244 of the Circuit Analysis Reference Manual for new the new syntax. 3.4 Constraint Check The CONSTRAINT primitive now allows you to specify RELEASETIME parameters. In addition, it supports distinct LO and HI level SETUP and HOLD time specifications. See Section 5.1.1.11.3 "Constraint Checker" on page 245 of the Circuit Analysis Reference Manual for the new syntax. 3.5 Limits on Mutual Inductance The limits on mutual inductance (often called the coupling coefficient) for K devices has been changed. The old limits were: 0 < x < 1 The new limits are: -1 <= x <= 1 Note that besides the extension from 0 to -1, the range now includes the extremes. 3.6 Using the charge storage feature of PSpice digital simulation The ability to model charge storage on digital nets is new for PSpice version 5.3, and is not included in the 5.3 documentation. This feature is mainly useful for engineers who are designing dynamic MOS integrated circuits. In such circuits it is common for the designer to temporarily store a one or zero on a net by driving the net to the appropriate voltage and then turning off the drive. The charge which is trapped on the net causes the net's voltage to remain unchanged for some time after the net is no longer driven. The technique is not normally used on PCB nets because sub-nanoamp input and output leakage currents would be required, as well as low coupling from adjacent signals. PSpice models the stored charge nets using a simplified "switch-level" simulation technique. A normalized (with respect to power supply) charge or discharge current is calculated for each output or transfer gate attached to the net. This current, divided by the netÆs total capacitance, is integrated and recalculated at intervals which are appropriate for the particular net. The net's digital level is determined by the normalized voltage on the net. Only the digital level (1, 0, R, F, X) on the net is used by device inputs attached to the net. This technique allows accurate simulation of networks of transfer gates and capacitive loads. The sharing of charge among several nets which are connected by transfer gates is handled properly because the simulation method calculates the charge transferred between the nets, and maintains a floating-point value for the charge on the net (not just a one or zero). Because of the increased computation, it takes PSpice longer to simulate charge storage nets than normal digital nets. Charge storage nets are simulated much faster than analog nets, however. In order for PSpice to decide which nets (if any) should be simulated as charge storage nets we have added three new model parameters to the digital I/O model (model type UIO). They are: Parameter Description Default Value ______________________________________________________________ INR Input leakage resistance 30Kohm DRVZ Output Z-state leakage 250Kohm resistance TSTOREMN Minimum storage time for net 1.0mSec to be simulated as a charge storage net. PSpice will simulate charge storage only for a net which has some devices attached to it which can be high Z, and which has a storage time greater than or equal to the smallest TSTOREMN of all inputs attached to the net. The storage time is calculated as the total capacitance (sum of all INLD and OUTLD values for attached inputs and outputs) multiplied by the total leakage resistance for the net (the parallel combination of all INR and DRVZ values for attached inputs and outputs). The default values provided by the UIO model will not allow most user circuits, even those which use non-MicroSim libraries of digital devices, to use the charge storage simulation techniques. This is appropriate, since these libraries are usually for PCB-based designs. 4.0 CMOS Power Supplies The CD4000 CMOS models now use different default power supply nodes: $G_CD4000_VDD and $G_CD4000_VSS. The voltage on these nodes can now be set directly by adding a .PARAM statement to your circuit. 4.1 Specifying Your Own Power Supply Designs using CD4000 devices often require power supply voltages other than, or in addition to, the default 5.0 volts supplied by CD4000_PWR. The Digital Library offers two methods for changing the power supply voltage on CD4000 series CMOS parts. For details on both methods, refer to Section 7.3.2 of the Circuit Analysis User's Guide (page 123). 5.0 Digital Device I/O Model Parameter Updates Non-zero values of INLD and OUTLD will now cause nets with tri-state or bidirectional transfer gates to be simulated as charge storage nets. 6.0 Remodeled Digital Devices and Timing Capabilities The Digital Library for version 5.3 contains many remodeled devices. Most of the complex sequential device models, such as counters and shift registers, now use the Logic Expression (LOGICEXP), Pin-to-Pin Delay (PINDLY), and Constraint Checking (CONSTRAINT) primitives, which were introduced in version 5.2. These new models offer improved readability, improved timing accuracy, and complete checking of setup/hold times and pulse widths. Any timing violations on these models are reported in detail as warning messages to the PSpice output file (".out"), and to the Probe data file (".dat") for use by Probe (currently, only PC/Windows Probe will display these messages). These warning messages are discussed further in the next section of this "readme" file, and also in Section 1.4 ".OPTIONS Command." A side benefit of the new Digital Library models is that they will NOT generate X states (unknowns) on the output when their timing constraints are violated. This new behavior makes it possible for your simulations to run to completion even when there are violations, without having everything "lock up" with X states. This can be very helpful early in the design process when circuit timing is a lesser concern than just getting the basic functionality to check out. It is important to note that, when PSpice reports timing constraint violations, the actual behavior of the circuit (despite the absence of X states) should be considered "possibly incorrect." The only sure way to obtain the full degree of accuracy embodied in the model is to resolve the timing issues by making appropriate circuit and/or stimulus changes, effectively removing all violation conditions. Also note that any circuits or library subcircuits that use flip-flop or latch primitives (DFF, JKFF, SRFF, or DLTCH) will continue to generate X states when their timing specifications are violated. They will also produce warning messages. This is inconsistent with the behavior of the Constraint Checking primitive, and will be addressed in a future release. 7.0 Simulation Condition Messages PSpice will produce warning messages in various situations, such as those that originate from the digital CONSTRAINT devices monitoring timing relationships of digital nodes. These messages are directed to the PSpice output file and/or to the Probe data file for use by Probe (currently, only PC/Windows Probe will display these messages). Options are available for controlling where, and how many of these messages are generated, as summarized in section 9.7 (starting on page 193) of the Circuit Analysis User's Guide. In version 5.3, messages describing "Net Conflicts" and "Suppressed Glitches" will NOT be produced by PSpice. All other Hazards and Timing Violations will generate messages, by default. 8.0 Charge Conservation For MOSFETs the capacitance model has been changed to conserve charge. This change affects the level 1, 2, and 3 models. The level 4 (BSIM) model has its own capacitance model which already conserves charge and remains unchanged. The Meyer equations for levels 1, 2, and 3 were replaced by the Yang-Chatterjee equations which are described in: "An investigation of the Charge Conservation Problem for MOSFET Circuit Simulation" by Ping Yang, Berton Epler and Pallab Chatterjee, IEEE Journal of Solid-State Circuits, vol. SC-18 no. 1, February 1983. Care was taken to see that (all) the charges are continuous across the boundaries. The resulting behavior matches closely the Meyer model. The main difference is that charge is now conserved. ********************************************************************* PROBE ********************************************************************* 1.0 Probe - New menu structure Information about all the changes in the Windows Probe menus can be found in Chapter 6 of the Circuit Analysis Reference Manual. See the page numbers referenced below to find out information about each main menu and the items within them. File Menu handles all of the file manipulation: opening plot windows and files, closing files, printing, and logging commands. (Page 328) Edit Menu provides commands to delete or modify objects. (Page 332) Trace Menu allows adding traces, creating macros, and evaluating goal functions on a single section of data. (Page 332) Plot Menu allows you to switch to a different analysis type, add and delete plots, and modify the X and Y axes. (Page 340) Zoom Menu provides a quick and simple, visual way to change the X and Y ranges of the current plot. (Page 343) Tools Menu allows you to add additional information to the plot window, to save and restore the display, and to configure Probe. (Page 344) Window Menu allows you to perform operations on plot windows. The Window Menu is currently not available for OpenWindows Probe. (Page 347) Help Menu allows you to get user identification and copyright information. (Page 348)